With the growing complexity of designs for VLSI integrated circuit chips, there is an ever increasing need for improvements in methods of testing such chips. Because it is not practical to exhaustively test ail the logic and memory circuits on such a chip, a suite of test vectors is typically selected that will exercise the chip sufficiently to expose a relatively high percentage of possible faults. Use of such a suite in testing manufactured chips then gives a high probability that ail existing faults will be detected.
In developing a suitable test-vector suite, it is well known to evaluate a given test vector with respect to a given fault in a simulated circuit by applying the test vector to the inputs of the circuit both with and without the fault and comparing the outputs from the circuit. The test vector has detected the fault if the outputs are different, but not if the outputs are the same.
Fault simulation, then, uses the techniques of logic simulation with the addition of fault injection and output comparison. Such simulation can require large amounts of data handling for complex circuits. For this reason, it has been useful to augment the computing power of existing computers to handle the additional computing load within a reasonable time. Devices to accomplish this task are known as hardware accelerators. One such hardware accelerator for use in circuit simulation is disclosed in U.S. Pat. No. 5,093,920. Such accelerator includes a number of separate processors connected in pipeline fashion with the simulation being carried out with each processor performing part of the overall simulation algorithm. The processors communicate by passing messages to each other relating to "events" occurring in the circuit being simulated. An event is a change in state of one of the elements in the circuit, for example, the change in state of the output of an AND gate from "0" to "1". Simulation is initiated by injecting messages into the pipeline to simulate events occurring on the inputs of the circuit when a test vector is applied to such inputs. Each event can give rise to subsequent events in the circuit in a recursive fashion. When the effects of all such events have been propagated through the simulated circuit, the outputs of the circuit for such test vector are logged.
One method of simulating multiple faults in a circuit includes simulating the circuit without faults (the "good" circuit) with a suite of test vectors to determine the output of such circuit for each test vector, then injecting a fault (thereby creating a "faulty" circuit), repeating the simulation and comparing the outputs to determine which of the vectors detected the fault. If it is desired to simulate a large number of faults and a large suite of test vectors, such procedure can be extremely time consuming and, therefore, impractical for complex circuits. A commonly practiced alternative is to perform a concurrent simulation of the good circuit and a number (e.g., 1000) of faulty circuits. If organized properly, such concurrent simulation saves repeated simulation of those pans of the good circuit that are not affected by a given fault. Concurrent fault simulation in a pipeline hardware accelerator is described in "Fault Simulation in a Pipelined Multiprocessor System," by Prathima Agrawal et al. in the Proceedings of the IEEE 1989 International Test Conference, p.727. Concurrent simulation is described also in U.S. Pat. No. 4,769,817.
An additional problem in simulating the effect of circuit faults is the simulation of the effect of such faults on functional circuits, such as memory blocks, programmable gate arrays and other multiple input, multiple output combinational or sequential circuits. Memory blocks, such as registers, random-access memories and read-only memories, are typical in VLSI circuits and fault simulation of such circuits cannot be considered complete without taking such memory blocks into account. It is not always necessary to consider faults in the memory blocks or other functional circuits themselves; it is often sufficient to just simulate the effects on memory blocks of faults external to the memory blocks. The simulation of memory blocks in circuits is described in "Modeling and Simulation of Functional Memory Blocks in the MARS Accelerator" by Prathima Agrawal et al. in the Proceedings of the International Workshop on Hardware Accelerators, Oxford, England 1989. Fault simulation of memory blocks is also alluded to briefly in such paper and in the paper referred to in the previous paragraph.
When concurrent fault simulation is being performed for a complex circuit, with or without functional circuits, in a pipelined hardware accelerator, it is desirable to find efficient ways of handling the data storage and processing problems. Such problems are exacerbated when functional circuits, such as memory blocks, are included because the effects of external faults on data stored in the memory block must be tracked. Much of the processing in fault simulation involves searching for data records relating to the effects of given faults on the various circuit elements. It is therefore desirable to minimize the time for such searches, and the amount of storage needed for such records, by eliminating records created early in a simulation that are no longer needed. Accordingly, it is an object of the invention to achieve an efficient method and apparatus for controlling the data records for concurrent fault simulation in a pipeline hardware accelerator. It is a further object of the invention to extend such method and apparatus for such fault simulation wherein functional circuits such as memory blocks are included in the circuit being simulated. Other objects of the invention will be apparent from the following specification and attached drawings.